TLE9261-3QX Datasheet, PDF (175/186 Pages) Infineon Technologies AG – Dedicated Data Sheets are available for the different product variants

15.7
Electrical Characteristics
TLE9261-3QX
Serial Peripheral Interface
Table 36 Electrical Characteristics
V_S = 5.5 V to 28 V, T_j = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Min.
Values
Unit Note /
Typ. Max.
Test Condition
Number
SPI frequency
Maximum SPI frequency
f_SPI,max
–
–
SPI Interface; Logic Inputs SDI, CLK and CSN
4.0
MHz ¹⁾
P_16.7.1
H-input Voltage Threshold V_IH
L-input Voltage Threshold
V_IL
Hysteresis of input Voltage V_IHY
Pull-up Resistance at pin CSN R_ICSN
Pull-down Resistance at pin R_ICLK/SDI
SDI and CLK
Input Capacitance at pin CSN, C_I
SDI or CLK
–
–
0.7* V
V_CC1
0.3* –
–
V
V_CC1
–
0.12* –
V
V_CC1
20
40
80
kΩ
20
40
80
kΩ
–
10
–
pF
–
P_16.7.2
–
P_16.7.3
1)
P_16.7.4
V_CSN = 0.7 x V_CC1
V_SDI/CLK =
0.2 x V_CC1
1)
P_16.7.5
P_16.7.6
P_16.7.7
Logic Output SDO
H-output Voltage Level
V_SDOH
V_CC1 - V_CC1 - –
0.4
0.2
V
I_DOH = -1.6 mA
P_16.7.8
L-output Voltage Level
Tristate Leakage Current
Tristate Input Capacitance
Data Input Timing¹⁾
V_SDOL
I_SDOLK
C_SDO
–
0.2
0.4
V
I_DOL = 1.6 mA
P_16.7.9
-10 –
10
µA
V_CSN = V_CC1;
P_16.7.10
0 V < V_DO < V_CC1
–
10
15
pF
1)
P_16.7.11
Clock Period
Clock High Time
Clock Low Time
Clock Low before CSN Low
CSN Setup Time
CLK Setup Time
Clock Low after CSN High
SDI Set-up Time
SDI Hold Time
Input Signal Rise Time at pin
SDI, CLK and CSN
t_pCLK
t_CLKH
t_CLKL
t_bef
t_lead
t_lag
t_beh
t_DISU
t_DIHO
t_rIN
250 –
125 –
125 –
125 –
250 –
250 –
125 –
100 –
50
–
–
–
–
ns –
–
ns –
–
ns –
–
ns –
–
ns –
–
ns –
–
ns –
–
ns –
–
ns –
50
ns –
P_16.7.12
P_16.7.13
P_16.7.14
P_16.7.15
P_16.7.16
P_16.7.17
P_16.7.18
P_16.7.19
P_16.7.20
P_16.7.21
Input Signal Fall Time at pin t_fIN
SDI, CLK and CSN
–
–
50
ns –
P_16.7.22
Delay Time for Mode
Changes²⁾
t_Del,Mode
–
–
6
µs includes internal P_16.7.23
oscillator tolerance
Data Sheet
175
Rev. 1.1, 2014-09-26