XC2288H_11 Datasheet, PDF (144/151 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance

XC2288H, XC2289H
XC2000 Family / High Line
Electrical Parameters
Table 42 JTAG Interface Timing for Upper Voltage Range (cont’d)
Parameter
Symbol
Values
Unit Note /
Min. Typ. Max.
Test Condition
TCK low time
t₃ SR 16
−
−
ns
TCK clock rise time
t₄ SR −
−
8
ns
TCK clock fall time
t₅ SR −
−
8
ns
TDI/TMS setup to TCK t₆ SR 6
−
−
ns
rising edge
TDI/TMS hold after TCK t₇ SR 6
−
−
ns
rising edge
TDO valid from TCK falling t₈ CC −
edge (propagation delay)²⁾
25
29
ns
TDO high impedance to t₉ CC −
valid output from TCK
falling edge³⁾²⁾
25
29
ns
TDO valid output to high t₁₀ CC −
impedance from TCK
falling edge²⁾
25
29
ns
TDO hold after TCK falling t₁₈ CC 5
−
−
ns
edge²⁾
1) Under typical conditions, the JTAG interface can operate at transfer rates up to 20 MHz.
2) The falling edge on TCK is used to generate the TDO timing.
3) The setup time for TDO is given implicitly by the TCK cycle time.
Table 43 is valid under the following conditions: C_L= 20 pF; voltage_range= lower
Table 43 JTAG Interface Timing for Lower Voltage Range
Parameter
Symbol
Values
Unit Note /
Min. Typ. Max.
Test Condition
TCK clock period
t₁ SR 50
−
−
ns
TCK high time
t₂ SR 16
−
−
ns
TCK low time
t₃ SR 16
−
−
ns
TCK clock rise time
t₄ SR −
−
8
ns
TCK clock fall time
t₅ SR −
−
8
ns
TDI/TMS setup to TCK t₆ SR 6
−
−
ns
rising edge
Data Sheet
144
V1.3, 2011-07