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| XC2288H_11 Datasheet, PDF (132/151 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance | |||
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XC2288H, XC2289H
XC2000 Family / High Line
Electrical Parameters
tpAB
tpC
tpD
tpE
tpF
CLKOUT
t21
t11
ALE
A23-A0,
BHE, CSx
t11/t12/t14
RD
WR(L/H)
D15-D0
(read)
D15-D0
(write)
Address
t10
t24
t20
t31
t30
Data In
t16
t25
Data Out
MC_X_EBCDEMUX
Figure 25 Demultiplexed Bus Cycle
4.7.5.1 Bus Cycle Control with the READY Input
The duration of an external bus cycle can be controlled by the external circuit using the
READY input signal. The polarity of this input signal can be selected.
Synchronous READY permits the shortest possible bus cycle but requires the input
signal to be synchronous to the reference signal CLKOUT.
An asynchronous READY signal puts no timing constraints on the input signal but incurs
a minimum of one waitstate due to the additional synchronization stage. The minimum
Data Sheet
132
V1.3, 2011-07
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