XC2288H_11 Datasheet, PDF (139/151 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance

XC2288H, XC2289H
XC2000 Family / High Line
Electrical Parameters
4.7.7 FlexRay Interface Timing
The following parameters are applicable to the FlexRay channels.
Notes
1. These parameters are not subject to production test but verified by design and/or
characterization.
2. Valid for FlexRay operation frequency 80 MHz.
3. Valid for pad Driver_Strength=Strong; Driver_Edge=Sharp.
4. Must use double pad (see Chapter 2.1) when operated at 3.3 V.
5. Operating Conditions apply.
Table 39 ERAY FlexRay Interface Timing
Parameter
Symbol
Values
Unit Note /
Min. Typ. Max.
Test Condition
Time span from last BSS
to FES without the
influence of quartz
tolerance (d10Bit_TX)¹⁾
t₆₀ CC
997.75 −
1002.2 ns
5
f_OSC= 20 MHz;
C_L≤ 25 pF
TxD data valid from
t_{61_minus_} −
−
1.5
ns C_L≤ 25 pF
fsample flip flop txd_reg _t62 CC
=> TxDA, TxDB
(dTxAsym)²⁾³⁾
Time span between last
BSS and FES without
influence of quartz
tolerance (d10Bit_RX)¹⁾⁴⁾
t₆₃ SR
966.5 −
1046.0 ns f_OSC= 20 MHz
RxD capture by fsample t_{64_minus_} −
−
3.5 ns
(RxDA/RxDB =>
t65 ^CC
sampling flip-flop)
(dRxAsym)⁴⁾
1) PLL jitter included.
2) Refers to delays caused by the asymmetries of the output drivers of the digital logic and the GPIO pad drivers.
Quartz tolerance and PLL jitter are not included.
3) TxD output drivers have an asymmetry of rising and falling edges of |t_F - t_R| ≤ 1 ns.
4) Valid for output slopes of the Bus Driver of dRxSlope ≤ 5 ns at C_L = 15pF, 20% x V_DDP to 80% x V_DDP, according
to the FlexRay Electrical Physical Layer Specification V2.1 B.
Data Sheet
139
V1.3, 2011-07