XC2288H_11 Datasheet, PDF (141/151 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance

XC2288H, XC2289H
XC2000 Family / High Line
Electrical Parameters
4.7.8 Debug Interface Timing
The debugger can communicate with the XC228xH either via the 2-pin DAP interface or
via the standard JTAG interface.
Debug via DAP
The following parameters are applicable for communication through the DAP debug
interface.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Note: Operating Conditions apply.
Table 40 is valid under the following conditions: C_L= 20 pF; voltage_range= upper
Table 40 DAP Interface Timing for Upper Voltage Range
Parameter
DAP0 clock period¹⁾
DAP0 high time
DAP0 low time¹⁾
DAP0 clock rise time
DAP0 clock fall time
DAP1 setup to DAP0
rising edge
Symbol
Min.
t₁₁ SR 25
t₁₂ SR 8
t₁₃ SR 8
t₁₄ SR −
t₁₅ SR −
t₁₆ SR 3
Values
Typ. Max.
−
−
−
−
−
−
−
4
−
4
−
−
Unit Note /
Test Condition
ns
ns
ns
ns
ns
ns pad_type= high
speed ²⁾
6
−
−
ns pad_type= stan
dard
DAP1 hold after DAP0 t₁₇ SR 4
−
−
ns pad_type= high
rising edge
speed ²⁾
6
−
−
ns pad_type= stan
dard
DAP1 valid per DAP0
t₁₉ CC 19
21
−
clock period³⁾
ns pad_type= high
speed ²⁾
17
20
−
ns pad_type= stan
dard
1) See the DAP chapter for clock rate restrictions in the Active::IDLE protocol state.
2) Available high speed pins can be found in the pin definitions table in chapter 2.
3) The Host has to find a suitable sampling point by analyzing the sync telegram response.
Data Sheet
141
V1.3, 2011-07