ICS1893AFLF Datasheet, PDF (96/136 Pages) Integrated Device Technology – 3.3-V 10Base-T/100Base-TX Integrated PHYceiver™

ICS1893AF Data Sheet - Release
Chapter 8 Management Register Set
8.14 Register 19: Extended Control Register 2
The Extended Control Register provides more refined control of the internal ICS1893AF operations.
Note:
1. For an explanation of acronyms used in Table 8-20, see Chapter 1, “Abbreviations and Acronyms”.
2. During any write operation to any bit in this register, the STA must write the default value to all
Reserved bits.
Table 8-21. Extended Control Register (register [0x13])
Bit
Definition
When Bit = 0
When Bit = 1
19.15 Node/Repeater Mode
19.14 Hardware/Software
Mode
19.13 Remote Fault
19.12 ICS reserved
19.11 ICS reserved
19.10 ICS reserved
19.9 ICS reserved
19.8 ICS reserved
19.7 Twisted Pair Tri-State
Enable, TPTRI
19.6 ICS reserved
19.5 ICS reserved
19.4 ICS reserved
19.3 ICS reserved
19.2 ICS reserved
19.1 ICS reserved
19.0 Automatic 100Base-TX
Power Down
Node mode
Hardware mode
Repeater mode
Software mode
No faults detected
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Twisted Pair Signals
are not Tri-Stated or
No effect
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Do not automatically
power down
Remote fault
detected
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Twisted Pair Signals
are Tri-Stated
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Power down
automatically
Ac-
cess
RO
RO
RO
RW
RW
RO
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
SF De- Hex
fault
–
0†
4
–
1†
–
0
–
0
–
0
0
–
0
–
0
–
0
–
0
0
–
0
–
0
–
0
–
0
1
–
0
–
0
–
1
† The default is the state of this pin at reset.
ICS1893AF, Rev D 10/26/04
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
96
October, 2004