ICS1893AFLF Datasheet, PDF (115/136 Pages) Integrated Device Technology – 3.3-V 10Base-T/100Base-TX Integrated PHYceiver™

ICS1893AF Data Sheet - Release
Chapter 10 DC and AC Operating Conditions
10.5.2 Timing for Transmit Clock (TXCLK) Pins
Table 10-9 lists the significant time periods for signals on the Transmit Clock (TXCLK) pins for the various
interfaces. Figure 10-3 shows the timing diagram for the time periods.
Table 10-9. Transmit Clock Timing
Time
Period
Parameter
t1 TXCLK Duty Cycle
t2a TXCLK Period
t2b TXCLK Period
Conditions
–
100M MII (100Base-TX)
10M MII (10Base-T)
Min. Typ. Max. Units
35 50 65 %
– 40 – ns
– 400 – ns
Figure 10-3. Transmit Clock Timing Diagram
t1
TXCLK
t2x
ICS1893AF, Rev. D 10/26/04
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
115
October, 2004