ICS1893AFLF Datasheet, PDF (90/136 Pages) Integrated Device Technology – 3.3-V 10Base-T/100Base-TX Integrated PHYceiver™

ICS1893AF Data Sheet - Release
Chapter 8 Management Register Set
8.12.5 100Base PLL Lock Error (bit 17.9)
The Phase-Locked Loop (PLL) Lock Error bit indicates to an STA whether the ICS1893AF has ever
experienced a PLL Lock Error. A PLL Lock Error occurs when the PLL fails to lock onto the incoming
100Base data stream. If this bit is set to a logic:
• Zero, it indicates that a PLL Lock Error has not occurred since either the last read or reset of this register.
• One, it indicates that a PLL Lock Error has occurred since either the last read or reset of this register.
This bit is a latching high bit. (For more information on latching high and latching low bits, see Section
8.1.4.1, “Latching High Bits” and Section 8.1.4.2, “Latching Low Bits”.)
Note: This bit has no definition in 10Base-T mode.
8.12.6 False Carrier (bit 17.8)
The False Carrier bit indicates to an STA the detection of a False Carrier by the ICS1893AF in 100Base
mode.
A False Carrier occurs when the ICS1893AF begins evaluating potential data on the incoming 100Base
data stream, only to learn that it was not a valid /J/K/. If this bit is set to a logic:
• Zero, it indicates a False Carrier has not been detected since either the last read or reset of this register.
• One, it indicates a False Carrier was detected since either the last read or reset of this register.
This bit is a latching high bit. (For more information on latching high and latching low bits, see Section
8.1.4.1, “Latching High Bits” and Section 8.1.4.2, “Latching Low Bits”.)
Note: This bit has no definition in 10Base-T mode.
8.12.7 Invalid Symbol (bit 17.7)
The Invalid Symbol bit indicates to an STA the detection of an Invalid Symbol in a 100Base data stream by
the ICS1893AF.
When the ICS1893AF is receiving a packet, it examines each received Symbol to ensure the data is error
free. If an error occurs, the port indicates this condition to the MAC/repeater by asserting the RXER signal.
In addition, the ICS1893AF sets its Invalid Symbol bit to logic one. Therefore, if this bit is set to a logic:
• Zero, it indicates an Invalid Symbol has not been detected since either the last read or reset of this
register.
• One, it indicates an Invalid Symbol was detected since either the last read or reset of this register.
This bit is a latching high bit. (For more information on latching high and latching low bits, see Section
8.1.4.1, “Latching High Bits” and Section 8.1.4.2, “Latching Low Bits”.)
Note: This bit has no definition in 10Base-T mode.
ICS1893AF, Rev D 10/26/04
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
90
October, 2004