ICS1893AFLF Datasheet, PDF (124/136 Pages) Integrated Device Technology – 3.3-V 10Base-T/100Base-TX Integrated PHYceiver™

ICS1893AF Data Sheet - Release
Chapter 10 DC and AC Operating Conditions
10.5.11 100M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission)
Table 10-18 lists the significant time periods for the 100M MII carrier assertion/de-assertion during
half-duplex transmission. The time periods consist of timings of signals on the following pins:
• TXEN
• TXCLK
• CRS
Figure 10-12 shows the timing diagram for the time periods.
Table 10-18. 100M MII Carrier Assertion/De-Assertion (Half-Duplex Transmission Only)
Time
Period
Parameter
t1 TXEN Sampled Asserted to CRS Assert
t2 TXEN De-Asserted to CRS De-Asserted
Condi- Min.
tions
0
0
Typ.
3
3
Max. Units
4 Bit times
4 Bit times
Figure 10-12. 100M MII Carrier Assertion/De-Assertion Timing Diagram
(Half-Duplex Transmission Only)
t2
TXEN
TXCLK
CRS
t1
ICS1893AF, Rev D 10/26/04
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
124
October, 2004