ICS1893AFLF Datasheet, PDF (1/136 Pages) Integrated Device Technology – 3.3-V 10Base-T/100Base-TX Integrated PHYceiver™

Integrated Circuit Systems, Inc.
ICS1893AF
Document Type: Data Sheet
Document Stage: Release
3.3-V 10Base-T/100Base-TX Integrated PHYceiver™
General
The ICS1893AF is a lower cost, re-packaged version of the
ICS1893Y-10. The ICS1893AF is a fully integrated, Physical
Layer device (PHY) that is compliant with both the 10Base-T
and 100Base-TX CSMA/CD Ethernet Standard, ISO/IEC
8802-3. The ICS1893AF uses the same proven silicon as
the ICS1893Y-10 but offers a lower cost solution by using a
lower cost 300 mil. 48-lead SSOP package.
The ICS1893AF uses the same twisted-pair transmit and
receive circuits as the ICS1893Y-10, and the same
recommended board layout techniques apply to the
ICS1893AF.
The ICS1893AF is intended for Node applications using the
standard MII interface to the MAC.
All differences in the ICS1893AF / ICS1893Y-10 Feature Set
are listed in the Comparison Table on page 14.
Features
• Single 3.3V power supply
• Supports category 5 cables with attenuation in excess of
24dB at 100 MHz.
• DSP-based baseline wander correction to virtually
eliminate killer packets
• Low-power, 0.35-micron CMOS (typically 400 mW)
• Single-chip, fully integrated PHY provides PCS, PMA,
PMD, and AUTONEG sublayers of IEEE standard
• 10Base-T and 100Base-TX IEEE 802.3 compliant
• Clock or crystal supported
• Media Independent Interface (MII) supported
• Managed or Unmanaged Applications
• 10M or 100M Half and Full Duplex Modes
• Auto-Negotiation with Parallel detection for Legacy
products
• Fully integrated, DSP-based PMD includes:
– Adaptive equalization and baseline wander correction
– Transmit wave shaping and stream cipher scrambler
– MLT-3 encoder and NRZ/NRZI encoder
• Loopback mode for Diagnostic Functions
• Small footprint 48-pin 300 mil SSOP package. Available in
Industrial Temperature and Lead Free packaging.
ICS1893AF Block Diagram
10/100 MII
MAC
Interface
MII Serial
Management
Interface
Interface
MUX
MII
Extended
Register
Set
PCS
• Framer
• CRS/COL
Detection
• Parallel to Serial
• 4B/5B
Low-Jitter
Clock
Synthesizer
Clock
100Base-T
PMA
• Clock Recovery
• Link Monitor
• Signal Detection
• Error Detection
10Base-T
TP_PMD
• MLT-3
• Stream Cipher
• Adaptive Equalizer
• Baseline Wander
Correction
Configuration
and Status
Integrated
Switch
Auto-
Negotiation
Twisted-
Pair
Interface to
Magnetics
Modules and
RJ45
Connector
Power
LEDs and PHY
Address
ICS1893AF, Rev. F 05/13/10
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any information
being relied upon by the customer is current and accurate.
Octobe