ICS1893AFLF Datasheet, PDF (127/136 Pages) Integrated Device Technology – 3.3-V 10Base-T/100Base-TX Integrated PHYceiver™

ICS1893AF Data Sheet - Release
Chapter 10 DC and AC Operating Conditions
10.5.14 100M Media Independent Interface: Input-to-Carrier Assertion/De-Assertion
Table 10-21 lists the significant time periods for the 100M MDI input-to-carrier assertion/de-assertion. The
time periods consist of timings of signals on the following pins:
• TP_RX (that is, TP_RXP and TP_RXN)
• CRS
• COL
Figure 10-15 shows the timing diagram for the time periods.
Table 10-21. 100M MDI Input-to-Carrier Assertion/De-Assertion Timing
Time
Period
Parameter
Conditions Min.
t1 First Bit of /J/ into TP_RX to CRS Assert †
–
10
t2 First Bit of /J/ into TP_RX while
Transmitting Data to COL Assert †
Half-Duplex Mode 9
t3 First Bit of /T/ into TP_RX to CRS
De-Assert ‡
–
13
t4 First Bit of /T/ Received into TP_RX to
COL De-Assert ‡
Half-Duplex Mode 13
Typ. Max. Units
– 14 Bit times
– 13 Bit times
– 18 Bit times
– 18 Bit times
† The IEEE maximum is 20 bit times.
‡ The IEEE minimum is 13 bit times, and the maximum is 24 bit times.
Figure 10-15. 100M MDI Input to Carrier Assertion / De-Assertion Timing Diagram
First bit
First bit of /T/
TP_RX^†
t3
t1
CRS
COL
t2
t4
† _Shown
unscrambled.
ICS1893AF, Rev. D 10/26/04
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
127
October, 2004