STAC9752A Datasheet, PDF (89/106 Pages) Integrated Device Technology – AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK

STAC9752A/9753A
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
PC AUDIO
10. TESTABILITY
The STAC9752A/9753A has two test modes. One is for ATE in-circuit test and the other is restricted
for IDT’s internal use. STAC9752A/9753A enters the ATE in-circuit test mode if SDATA_OUT is
sampled high at the trailing edge of RESET#. Once in the ATE test mode, the digital AC-Link outputs
(BIT_CLK and SDATA_IN) are driven to a high impedance state. This allows ATE in-circuit testing of
the AC'97 controller. Use of the ATE test mode is the recommended means of removing the CODEC
from the AC-Link when another CODEC is to be used as the primary. This case will never occur dur-
ing standard operating conditions. Once either of the two test modes have been entered, the
STAC9752A/9753A must be issued another RESET# with all AC-Link signals held low to return to
the normal operating mode.
SYNC
0
0
1
1
Table 31. Test Mode Activation
SDATA_OUT
0
1
0
1
Description
Normal AC '97 operation
ATE Test Mode
IDT Internal Test Mode
Reserved
10.1. ATE Test Mode
ATE test mode allows for in-circuit testing to be completed at board level. For this to work, the out-
puts of the device must be driven to a high impedance state (Z). Internal pullups for digital I/O pins
must be disabled in this mode. This mode initiates on the rising edge of RESET# pin. Only a cold
reset will exit the ATE Test Mode.
Table 32. ATE Test Mode Operation
Pin Name
Pin # Function
Description
SDATA_OUT
5
1
Must be held high at the rising edge of RESET#
BIT_CLK
6
Z
SDATA_IN
8
Z
SYNC
10
0
Must be held low at rising edge of RESET#
RESET#
11
1
N.C.
31
Z
Always an input
N.C.
33
Z
Always an input
N.C.
34
Z
Always an input
GPIO0
43
Z
GPIO1
44
Z
CID0
45
Z
CID1
46
Z
EAPD
47
Z
SPDIF
48
Z
Note: Pins 31, 33, and 34 are NO CONNECTS.
IDT™
89
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
STAC9752A/9753A
V 1.5 1206