STAC9752A Datasheet, PDF (70/106 Pages) Integrated Device Technology – AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK

STAC9752A/9753A
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
PC AUDIO
7.2.5.
GPIO Pin Configuration Register (4Ch)
Default: 0003h
D15
D14
D7
D6
D13
D12
D11
Reserved
D5
D4
D3
Reserved
D10
D9
D2
D1
GC1
(GPIO1)
Bit(s)
15:2
1
Access Reset Value
Read Only
0
Read / Write
1
0
Read / Write
1
Name
Reserved
GC1
GC0
Description
Bit not used, should read back 0
0 = GPIO1 configured as output
1 = GPIO1 configured as input
0 = GPIO0 configured as output
1 = GPIO0 configured as input
D8
D0
GC0
(GPIO0)
7.2.6.
GPIO Pin Polarity/Type Register (4Eh)
Default: FFFFh
D15
D14
D7
D6
D13
D12
D11
Reserved
D5
D4
D3
Reserved
D10
D9
D8
D2
D1
D0
GP1
(GPIO1)
GP0
(GPIO0)
Bit(s) Access Reset Value
15:2 Read Only
0
1 Read / Write
1
0 Read / Write
1
Name
Reserved
GP1
GP0
Description
Bit not used, should read back 0
0 = GPIO1 Input Polarity Inverted, CMOS output drive.
1 = GPIO1 Input Polarity Non-inverted, Open-Drain output drive.
0 = GPIO0 Input Polarity Inverted, CMOS output drive.
1 = GPIO0 Input Polarity Non-inverted, Open-Drain output drive.
7.2.7.
GPIO Pin Sticky Register (50h)
Default: 0000h
D15
D7
Bit(s)
15:2
D14
D6
Access
Read Only
D13
D12
D11
Reserved
D5
D4
D3
Reserved
D10
D9
D8
D2
D1
D0
GS1 (GPIO1) GS0 (GPIO0)
Reset Value Name
Description
0
Reserved Bit not used, should read back 0
IDT™
70
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
STAC9752A/9753A
V 1.5 1206