STAC9752A Datasheet, PDF (41/106 Pages) Integrated Device Technology – AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK

STAC9752A/9753A
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
PC AUDIO
5.4.3.
5.4.4.
5.4.5.
5.4.6.
5.4.7.
SLOTREQ bits are always 0 in the following cases
• Fixed rate mode (VRA = 0)
• Inactive (powered down) ADC channel
SLOTREQ bits are only set to 1 by the CODEC in the following case
• Variable rate audio mode (VRA = 1) AND active (power ready) ADC AND a non-48KHz ADC
sample rate and CODEC does not need a sample
Slot 2: Status Data Port
The status data port delivers 16-bit control register read data.
Table 10. Status Data Port Bit Assignments
Bit
Description
19:4
Control Register Read Data
3:0
Reserved
Comments
Stuffed with 0s if tagged "invalid"
Stuffed with 0s
If Slot 2 is tagged invalid by AC‘97, then the entire slot will be stuffed with 0s by AC‘97.
Slot 3: PCM Record Left Channel
Audio input frame slot 3 is the left channel output of STAC9752A/9753A input MUX, post-ADC.
STAC9752A/9753A ADCs are implemented to support 20-bit resolution.
NOTE: The ADC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.
Slot 4: PCM Record Right Channel
Audio input frame slot 4 is the right channel output of STAC9752A/9753A input MUX, post-ADC.
STAC9752A/9753A ADCs are implemented to support 20-bit resolution.
NOTE: The ADC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.
Slot 5: NOT USED (Modem Line 1 ADC)
Audio input frame slot 5 is not used by the STAC9752A/9753A and is always stuffed with 0s.
Slot 6-9: ADC
The left and right ADC channels of the STAC9752A/9753A may be assigned to slots 6&9 by Regis-
ter 6Eh.
NOTE: The ADC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.
IDT™
41
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
STAC9752A/9753A
V 1.5 1206