STAC9752A Datasheet, PDF (64/106 Pages) Integrated Device Technology – AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK

STAC9752A/9753A
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
PC AUDIO
one of three secondary CODECs. The AMAP bit, D9, will return a 1 indicating that the CODEC sup-
ports the optional “AC’97 2.3 Compliant AC-Link Slot to Audio DAC Mappings”. The default condition
assumes that 00 is loaded in the DSA0 and DSA1 bits of the Extended Audio ID (Index 28h). With 00
in the DSA1 and DSA0 bits, the CODEC slot assignments are as per the AC’97 specification recom-
mendations. If the DSA1 and DSA0 bits do not contain 00, the slot assignments are as per the table
in the section describing the Extended Audio ID (Index 28h). The VRA bit, D0, will return a 1 indicat-
ing that the CODEC supports the optional variable sample rate conversion as defined by the AC’97
specification.
Bit
15:14
13:12
11:10
9:6
Name
ID [1,0]
Reserved
REV[1:0]
RSVD
Table 19. Extended Audio ID Register Functions
Access Reset Value
Function
Read only
variable
00 = XTAL_OUT grounded (Note Note:)
CID1#,CID0# = XTAL_OUT crystal or floating
Read only
00
Bits not used, should read back 00
Read only
10
Indicates CODEC is AC’97 Rev 2.3 compliant
Read only
0
Reserved
DAC slot assignment
If CID[1:0] = 00 then DSA[1:0] resets to 00
If CID[1:0] = 01 then DSA[1:0] resets to 01
If CID[1:0] = 10 then DSA[1:0] resets to 01
5:4 DSA [1,0] Read/Write
00
If CID[1:0] = 11 then DSA[1:0] resets to 10
3
RSVD Read only
2
SPDIF Read only
1
RSVD Read only
0
VRA
Read only
00 = left slot 3, right slot 4
01 = left slot 7, right slot 8
10 = left slot 6, right slot 9
11 = left slot 10, right slot 11
0
Reserved
1
0 = SPDIF pulled high on reset, SPDIF disabled
1 = default, SPDIF enabled (Note Note:)
0
Reserved
1
Variable sample rates supported (Always = 1)
Note: 1) External CID pin status (from analog), these bits are the logical inversion of the pin polarity (pin
45-46). These bits are zero if XTAL_OUT is grounded with an alternate external clock source (in
primary mode only). Secondary mode can either be through BIT CLK driven or 24MHz clock driver,
with XTAL_OUT floating.
Note: 2) If pin 48 is held high at powerup, this bit will be held to zero, to indicate the SPDIF is not available.
To disable SPDIF, use an 1KΩ - 1 0 KΩ external pullup resistor.
7.1.20.
Extended Audio Control/Status (2Ah)
Default: 0400h* (*default depends on CODEC ID)
D15
D14
VCFG
D7
D6
Reserved
D13
D12
Reserved
D5
D4
SPSA1
SPSA0
D11
D3
RSRVD
D10
SPCV
D2
SPDIF
D9
D8
Reserved
D1
D0
RSRVD VRA enable
IDT™
64
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
STAC9752A/9753A
V 1.5 1206