STAC9752A Datasheet, PDF (17/106 Pages) Integrated Device Technology – AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK

STAC9752A/9753A
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
PC AUDIO
2.2.3.
Clocks
BIT_CLK
SYNC
Figure 4. Clocks Timing
Tclk_low
Tclk_high
Tclk_period
Tsync_high
Tsync_low
Tsync_period
Parameter
BIT_CLK frequency
BIT_CLK period
BIT_CLK output jitter
BLT_CLK high pulse width (Note 1)
BIT_CLK low pulse width (Note 1)
SYNC frequency
SYNC period
SYNC high pulse width
SYNC low pulse width
Note: 1. Worst case duty cycle restricted to 45/55.
Symbol
Min Typ Max
- 12.288 -
Tclk_period
-
81.4
-
-
750
-
Tclk_high
36 40.7
45
Tclk_low
36 40.7
45
-
48.0
-
Tsync_period -
20.8
-
Tsync_high
-
1.3
-
Tsync_low
-
19.5
-
Units
MHz
ns
ps
ns
ns
KHz
µs
µs
µs
2.2.4.
STAC9752A/9753A Crystal Elimination Circuit and Clock Frequencies
The STAC9752A/9753A supports several clock frequency inputs as described in the following table.
In general, when a 24.576MHz crystal is not used, the XTALOUT pin should be tied to ground. This
short to ground configures the part into an alternate clock mode and enables an on board PLL.
CODEC Modes:
P = The STAC9752A/9753A as a Primary CODEC
S = The STAC9752A/9753A as a Secondary CODEC.
Table 1. Clock mode configuration
XTL_OUT Pin Config
XTAL
XTAL or open
XTAL or open
XTAL or open
short to ground
short to ground
CID1 Pin Config CID0 pin config
float
float
pulldown
pulldown
float
float
float
pulldown
float
pulldown
float
pulldown
Clock Source Input CODEC Mode
24.576MHz xtal
P
12.288MHz bit clk
S
12.288MHz bit clk
S
12.288MHz bit clk
S
14.31818MHz source
P
27MHz source
P
CODEC
ID
0
1
2
3
0
0
IDT™
17
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
STAC9752A/9753A
V 1.5 1206