STAC9752A Datasheet, PDF (39/106 Pages) Integrated Device Technology – AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK

STAC9752A/9753A
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
PC AUDIO
5.4.1.
Tag Phase
Data Phase
20.8 uS (48 kHZ)
SYNC
BIT_CLK
12.288 MHz
SDATA_IN
valid
Frame
slot1
slot2
slot(12) "0" "0" "0" 19
"0" 19
"0" 19
"0"
End of previous audio frame
Time Slot "Valid" Bits
("1" = time slot contains valid PCM data)
Slot 1
Slot 2
Slot 3
19
"0"
Slot 12
AC-Link are aware of the start of a new audio frame. On the next rising of BIT_CLK, the AC‘97
CODEC transitions SDATA_IN into the first bit position of slot 0 (“CODEC Ready” bit). Each new bit
position is presented to AC-Link on a rising edge of BIT_CLK, and subsequently sampled by the
AC‘97 Controller on the following falling edge of BIT_CLK. This sequence ensures that data transi-
tions and subsequent sample points for both incoming and outgoing data streams are time aligned.
Figure 18. Start of an Audio Input Frame
SYNC
detected
first
SDATA_OUT
bit of frame
SYNC
BIT_CLK
SDATA_IN
Codec
Ready
End of previous audio frame
slot1 slot2
SDATA_IN’s composite stream is MSB justified (MSB first) with all non-valid bit positions (for
assigned and/or unassigned time slots) stuffed with 0s by the AC‘97 CODEC. SDATA_IN data is
sampled on the falling edges of BIT_CLK.
Slot 0: TAG
Within slot 0, the first bit is a global bit (SDATA_IN slot 0, bit 15) which flags whether the AC‘97
CODEC is in the “CODEC Ready” state or not. If the “CODEC Ready” bit is a 0, this indicates that
the AC‘97 CODEC is not ready for normal operation. This condition is normal following the deasser-
tion of power on reset for example, while the AC‘97 CODEC’s voltage references settle. When the
AC-Link “CODEC Ready” indicator bit is a 1 it indicates that the AC-Link and AC‘97 CODEC control
and status registers are in a fully operational state. CODEC must assert “CODEC Ready” within
400 µs after it starts receiving valid SYNC pulses from the controller, to provide indication of connec-
tion to the link and Control/Status registers are available for access. The AC’97 Controller and
related software must wait until all of the lower four bits of the Control/Status Register, 26h, are set
IDT™
39
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
STAC9752A/9753A
V 1.5 1206