STAC9752A Datasheet, PDF (61/106 Pages) Integrated Device Technology – AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK

STAC9752A/9753A
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
PC AUDIO
7.1.17.
Audio Interrupt and Paging (24h)
Default: 0000h
D15
D14
D13
I4
I3
I2
D7
D6
D5
Reserved
Bit(s) Reset Value Access
Name
15
0
Read / Write
I4
14-13
0
Read Only
I3-I2
12
0
Read / Write
I1
11
0
Read / Write
I0
D12
D11
D10
D9
D8
I1
I0
Reserved
D4
D3
D2
D1
D0
PG3
PG2
PG1
PG0
Description
0 = Interrupt is clear
1 = interrupt is set
Interrupt event is cleared by writing a 1 to this bit.
The interrupt bit will change regardless of condition of interrupt
enable (I0) status. An interrupt in the GPI in slot 12 in the ACLink
will follow this bit change when interrupt enable (I0) is unmasked.
Interrupt Cause
00 = Reserved
01 = Sense Cycle Complete, sense info available.
10 = Change in GPIO input status
11 = Sense Cycle Complete and Change in GPIO input status.
These bits will reflect the general cause of the first interrupt event
generated. It should be read after interrupt status has been
confirmed as interrupting. The information should be used to scan
possible interrupting events in proper pages.
Sense Cycle
0 = Sense Cycle not in Progress
1 = Sense Cycle Start.
Writing a 1 to this bit causes a sense cycle start if supported. If
sense cycle is not supported this bit is read only.
Interrupt Enable
0 = Interrupt generation is masked.
1 = Interrupt generation is un-masked.
The driver should not un-mask the interrupt unless ensured by the
AC‘97 controller that no conflict is possible with modem slot 12 -
GPI functionality. Some AC’97 2.2 compliant controllers will not
likely support audio CODEC interrupt infrastructure. In either case,
Software should poll the interrupt status after initiating a sense
cycle and wait for Sense Cycle Max Delay to determine if an
interrupting event has occurred.
IDT™
61
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
STAC9752A/9753A
V 1.5 1206