STAC9752A Datasheet, PDF (25/106 Pages) Integrated Device Technology – AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK

STAC9752A/9753A
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
PC AUDIO
4. CONTROLLER, CODEC, AND AC-LINK
This section describes the physical and high-level functional aspects of the AC‘97 Controller to
CODEC interface, referred to as the AC-Link.
4.1. AC-Link Physical interface
The STAC9752A/9753A communicates with its companion Digital Controller via the AC-Link digital
serial interface. AC-Link has been defined to support connections between a single Controller and
up to four CODECs. All digital audio, modem and handset data streams, as well as all control (com-
mand/status) information are communicated over this serial interconnect, which consists of a clock
(BIT_CLK), frame synchronization (SYNC), serial data in (SDATA_IN), serial data out
(SDATA_OUT), and a reset (RESET#).
4.2. Controller to Single CODEC
The simplest and most common AC‘97 system configuration is a point-to-point AC-Link connection
between Controller and the STAC9752A/9753A, as illustrated in Figure 12.
Figure 12. AC-Link to its Companion Controller
Digital DC'97
Controller
SYNC
BIT_CLK
SDATA_OUT
SDATA_IN
RESET#
XTAL_IN
AC'97 Codec
XTAL_OUT
A primary CODEC may act as either a source or a consumer of the BIT_CLK, depending on the con-
figuration.
While RESET# is asserted, if a clock is present at the BIT_CLK pin for at least five cycles before
RESET# is de-asserted, then the CODEC is a consumer of BIT_CLK, and must not drive BIT_CLK
when RESET# is de-asserted. The clock is being provided by other than the primary CODEC, for
instance by the controller or an independent clock chip. In this case the primary CODEC must act as
a consumer of the BIT_CLK signal as if it were a secondary CODEC.
This clock source detection must be done each time the RESET# line is asserted. In the case of a
warm reset, where the clock is halted but RESET# is not asserted, the CODEC must remember the
clock source, and not begin generating the clock on the assertion of SYNC if the CODEC had previ-
ously determined that it was a consumer of BIT_CLK.
The STAC9752A/9753A uses the XTAL_OUT pin (Pin 3) and the CID0 and CID1 pins (Pins 45 & 46)
to determine its alternate clock frequencies. See section2.2.4: page 17 for additional information on
Crystal Elimination and for supported clock frequencies.
IDT™
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AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
STAC9752A/9753A
V 1.5 1206