STAC9752A Datasheet, PDF (32/106 Pages) Integrated Device Technology – AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK

STAC9752A/9753A
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
PC AUDIO
Table 4. AC-Link Output Slots (transmitted from the Controller)
Slot
12
12
10-11
10-12
Name
Modem IO control
CODEC IRQ
SPDIF Out
Double Rate Audio
Description
GPIO write port for modem Control
Can be used by CODEC if a modem CODEC is not present.
Optional AC-Link bandwidth for SPDIF output
Optional AC-Link bandwidth for 88.2 or 96KHz on L, C, R
channels
Table 5. The AC-Link Input Slots (transmitted from the CODEC)
Slot
0
1
2
3, 4
5
6-11
12
Name
SDATA_IN TAG
STATUS ADDR read port
STATUS DATA read port
PCM L&R ADC record
Modem Line 1 ADC
PCM ADC Record
GPIO Status
Description
MSBs indicate which slots contain valid data
MSBs echo register address; LSBs indicate which slots request data
16-bit command register read data
20-bit PCM data from Left and Right inputs
16-bit modem data from modem Line1 input
20-bit PCM data - Alternative Slots for Input
GPIO read port and interrupt status
5.2. AC-Link Serial Interface Protocol
The AC‘97 Controller signals synchronization of all AC-Link data transactions. The AC‘97 CODEC,
Controller, or external clock source drives the serial bit clock onto AC-Link, which the AC‘97 Control-
ler then qualifies with a synchronization signal to construct audio frames. SYNC, fixed at 48KHz, is
derived by dividing down the serial bit clock (BIT_CLK). BIT_CLK, fixed at 12.288 MHz, provides the
necessary clocking granularity to support twelve 20-bit outgoing and incoming time slots. AC-Link
serial data is transitioned on each rising edge of BIT_CLK. The receiver of AC-Link data (CODEC for
outgoing data and Controller for incoming data) samples each serial bit on the falling edges of
BIT_CLK.
The AC-Link protocol provides for a special 16-bit time slot (Slot 0) wherein each bit conveys a valid
tag for its corresponding time slot within the current audio frame. A 1 in a given bit position of slot 0
indicates that the corresponding time slot within the current audio frame has been assigned to a data
stream, and contains valid data. If a slot is tagged invalid, it is the responsibility of the source of the
data, (AC‘97 CODEC for the input stream, AC‘97 Controller for the output stream), to stuff all bit
positions with 0s during that slot’s active time.
SYNC remains high for a total duration of 16 BIT_CLKs at the beginning of each audio frame. The
portion of the audio frame where SYNC is high is defined as the “Tag Phase”. The remainder of the
audio frame where SYNC is low is defined as the “Data Phase”.
Additionally, for power savings, all clock, sync, and data signals can be halted. This requires that an
AC‘97 CODEC be implemented as a static design to allow its register contents to remain intact when
entering a power savings mode.
IDT™
32
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
STAC9752A/9753A
V 1.5 1206