STAC9752A Datasheet, PDF (16/106 Pages) Integrated Device Technology – AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK

STAC9752A/9753A
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
PC AUDIO
2.2. AC Timing Characteristics
(T_ambient = 25 °C, AVdd = 3.3V or 5V ± 5%, DVdd = 3.3V ± 5%, AVss = DVss = 0V; 75pF external
load for BIT_CLK and 60pF external load for SDATA_IN)
2.2.1.
Cold Reset
Figure 2. Cold Reset Timing
Tres_low
Trst2clk
RESET#
BIT_CLK
SDATA_IN
Ttri2actv
Ttri2actv
Parameter
RESET# active low pulse width
RESET# inactive to SDATA_IN or BIT_CLK active delay
RESET# inactive to BIT_CLK startup delay
BIT_CLK active to RESET# asserted (Not shown in diagram)
Symbol Min Typ Max Units
Tres_low 1.0
-
-
µs
Tri2actv
-
-
25
ns
Trst2clk .01628 -
400
µs
Tclk2rst 0.416 -
-
µs
Note: BIT_CLK and SDATA_IN are in a high impedance state during reset.
2.2.2.
Warm Reset
Figure 3. Warm Reset Timing
Tsync_high
Tsync_2clk
SYNC
BIT_CLK
Parameter
SYNC active high pulse width
SYNC inactive to BIT_CLK startup delay
Symbol Min Typ Max
Tsync_high 1.0 1.3
-
Tsync2clk 162.8 -
-
Units
µs
ns
IDT™
16
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
STAC9752A/9753A
V 1.5 1206