STAC9752A Datasheet, PDF (69/106 Pages) Integrated Device Technology – AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK

STAC9752A/9753A
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
PC AUDIO
7.2.2.
GPIO Pin Definitions
GPIO pins are programmable to have input/output functionality. The data values (status) for these
pins are all in one register with input/output configuration in a separate register. Control of GPIO pins
configured for output is achieved by setting the corresponding bit in output slot 12; status of GPIO
pins configured for input is returned on input slot 12. The CODEC must constantly set the GPIO pins
that are configured for output, based upon the value of the corresponding bit position of the control
slot 12. The CODEC should ignore output slot 12 bits that correspond to GPIO control pins config-
ured as inputs. The CODEC must constantly update status on input slot 12, based upon the logic
level detected at each GPIO pin configured for input. A GPIO output pin value that is written via slot
12 in the current frame won’t affect the GPIO status that is returned in that particular write frame.
This slot-12 based control/status protocol minimizes the latency and complexity, especially for
host-based Controllers and host data pump software, and provides high speed monitoring and con-
trol, above what could be achieved with command/status slots. For host-based implementations,
most AC‘97 registers can be shadowed by the driver in order to provide immediate response when
read by the processor, and GPIO pins configured as inputs should be capable of triggering an inter-
rupt upon a change of status.
The AC-Link request for GPIO pin status is always delayed by at least one frame time. Read-Mod-
ify-Writes across the AC-Link will thus incur latency issues and must be accounted for by the soft-
ware driver or AC‘97 Digital Controller firmware. PCI re-tries should be kept to a minimum wherever
possible.
7.2.3.
GPIO Pin Implementation
The GPIOs are set to a high impedance state on power-on or a cold reset. It is up to the AC‘97 Digi-
tal Controller to first enable the output after setting it to the desired state.
7.2.4.
Extended Modem Status and Control Register (3Eh)
Default: 0100h
D15
D14
D13
D7
D6
D5
Bit(s)
15:9
8
7:1
0
Access Reset Value
Read Only
0
Read / Write
1
Read Only
0
Read Only
0
D12
Reserved
D4
Reserved
Name
Reserved
PRA
Reserved
GPIO
D11
D10
D9
D3
D2
D1
Description
Bit not used, should read back 0
0 = GPIO powered up / enabled
1 = GPIO powered down / disabled
Bit not used, should read back 0
0 = GPIO not ready (powered down)
1 = GPIO ready (powered up)
D8
PRA
D0
GPIO
IDT™
69
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
STAC9752A/9753A
V 1.5 1206