STAC9752A Datasheet, PDF (42/106 Pages) Integrated Device Technology – AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK

STAC9752A/9753A
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
PC AUDIO
5.4.8.
Slots 7-8: Vendor Reserved
The left and right ADC channels of the STAC9752A/9753A may be assigned to slots 7&8 by Regis-
ter 6Eh.
NOTE: The ADC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.
5.4.9.
Slot 10 & 11: ADC
The left and right ADC channels of the STAC9752A/9753A may be assigned to slots 10&11 by Reg-
ister 6Eh.
NOTE: The ADC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.
5.4.10.
Slot 12: Reserved
AC-Link input frame slot 12 contains the GPIO status inputs and allows for audio interrupts. Slot 12
can be used by the AC’97 CODEC is a modem CODEC is not present.
5.5. AC-Link Interoperability Requirements and Recommendations
5.5.1.
“Atomic slot” Treatment of Slot 1 Address and Slot 2 Data
Command or Status Address and Data cannot be split across multiple AC-Link frames. The following
transactions require that valid Slot 1 Address and valid Slot 2 Data be treated as “atomic” (insepara-
ble) with Slot 0 Tag bits for Address and Data set accordingly (that is, both valid):
1. AC‘97 Digital Controller write commands to Primary CODECs
2. AC‘97 CODEC status responses
Whenever the AC‘97 Digital Controller addresses a Primary CODEC or an AC‘97 CODEC responds
to a read command, Slot 0 Tag bits should always be set to indicate actual Slot 1 and Slot 2 data
validity.
Table 11. Primary CODEC Addressing: Slot 0 Tag Bits
Function
AC‘97 Digital Controller
Primary Read Frame N,
SDATA_OUT
AC‘97 Digital Controller
Primary Write Frame N,
SDATA_OUT
AC‘97 CODEC Status Frame
N+1, SDATA_IN
Slot 0, bit 15
Slot 0, bit 14
Slot 0, bit 13 Slot 0, Bits 1-0
(Valid Frame) (Valid Slot 1 Address) (Valid Slot 2 Data) (CODEC ID)
1
1
0
00
1
1
1
1
1
00
1
00
IDT™
42
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
STAC9752A/9753A
V 1.5 1206