IC42S8200 Datasheet, PDF (54/76 Pages) Integrated Circuit Solution Inc – 1Meg x 8 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM

1+" 5& 
Read Cycle / Precharge Termination
T0
T1
T2
T3
T4
CLK
tCKS
CKE
tCS
CS
RAS
CAS
WE
A0-A9
A10
A11
tCHI
tCK
tCL
tCKA
tCH
tCS
tCH
tCS
tCH
tCS
tCH
tAS
tAH
ROW
tAS
tAH
ROW
tAS
tAH
BANK 0
(1)
COLUMN m
NO PRE
BANK 0
DQM
tCS
tQMD
tAC
I/O
tLZ
tRCD
tCAC
tRAS
tRC
<ACT 0>
<READ 0>
T5
T6
T7
T8
T9
ROW
BANK 0 OR 1
BANK 0
tCH
ROW
BANK 1
BANK 0
tAC
tOH
DOUT m
tAC
tOH
DOUT m+1
tHZ
tOH
DOUT m+2
tRQL
tRP
<PRE 0>
tRCD
tRAS
tRC
<ACT >
CAS latency = 2, burst length = 4
T10
(1)
COLUMN n
AUTO PRE
NO PRE
BANK 1
BANK 0
tCAC
<READ>
<READA>
Undefined
Don’t Care
Note 1: A8,A9 = Don't Care.
54
Integrated Circuit Solution Inc.
DR018-0A 07/10/2001