IC42S8200 Datasheet, PDF (34/76 Pages) Integrated Circuit Solution Inc – 1Meg x 8 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM

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Burst Data Interruption DQM Pin
(Write Cycle)
Burst data input can be temporarily interrupted (muted )
during a write cycle using the DQM pin. Regardless of the
CAS latency, as soon as the DQM pin goes HIGH, the
corresponding externally applied input data will no longer
be written to the device internal circuits. Subsequently, the
corresponding input continues to be muted as long as that
DQM pin remains HIGH.
The IC42S8200 will revert to accepting input as soon as
that pin is dropped to LOW and data will be written to the
device.
Since the DQM pin control the device input buffers only, the
cycle continues internally and, inparticular, incrementing
of the internal burst counter continues.
CLK
COMMAND
DQM
WRITE A0
tDMD=0
I/O0-I/O7
DIN A1 DIN A2 DIN A3
WRITE (CA=A, BANK 0) DATA MASK
CAS latency = 2, burst length = 4
Burst Read and Single Write
The burst read and single write mode is set up using the
mode register set command. During this operation, the
burst read cycle operates normally, but the write cycle only
writes a single data item for each write cycle. The CAS
latency and DQM latency are the same as in normal mode.
Don’t Care
CLK
COMMAND
I/O
CAS latency = 2, 3
34
WRITE A0
DIN A0
WRITE (CA=A, BANK 0)
Integrated Circuit Solution Inc.
DR018-0A 07/10/2001