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IC42S8200 Datasheet, PDF (1/76 Pages) Integrated Circuit Solution Inc – 1Meg x 8 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM
1+" 5& 
1Meg x 8 Bits x 2 Banks (16-MBIT)
SYNCHRONOUS DYNAMIC RAM
.EATURES
• Clock frequency: 166, 143, 125, 100 MHz
• .ully synchronous; all signals referenced to a
positive clock edge
• Two banks can be operated simultaneously and
independently
• Dual internal bank controlled by A11 (bank select)
• Single 3.3V power supply
• LVTTL interface
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• Auto refresh, self refresh
• 4096 refresh cycles every 128 ms
• Random column address every clock cycle
• Programmable +)5 latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and precharge
command
• Package 400mil 44-pin TSOP-2
DESCRIPTION
1+51's 16Mb Synchronous DRAM IC42S8200 is organized
as a 1Meg x 8-bit x 2-bank for improved performance. The
synchronous DRAMs achieve high-speed data transfer
using pipeline architecture. All inputs and outputs signals
refer to the rising edge of the clock input.
PIN CON.IGURATIONS
44-Pin TSOP-2
VCC 1
I/O0 2
GNDQ 3
I/O1 4
VccQ 5
I/O2 6
GNDQ 7
I/O3 8
VccQ 9
NC 10
NC 11
WE 12
CAS 13
RAS 14
CS 15
A11 16
A10 17
A0 18
A1 19
A2 20
A3 21
VCC 22
44 GND
43 I/O7
42 GNDQ
41 I/O6
40 VCCQ
39 I/O5
38 GNDQ
37 I/O4
36 VCCQ
35 NC
34 NC
33 DQM
32 CLK
31 CKE
30 NC
29 A9
28 A8
27 A7
26 A6
25 A5
24 A4
23 GND
PIN DESCRIPTIONS
A0-A11
A0-A10
A11
A0-A8
I/O0 to I/O7
CLK
CKE
CS
RAS
Address Input
Row Address Input
Bank Select Address
Column Address Input
Data I/O
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
CAS
WE
DQM
Vcc
GND
VccQ
GNDQ
NC
Column Address Strobe Command
Write Enable
Input/Output Mask
Power
Ground
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
1
DR018-0A 07/10/2001