IC42S8200 Datasheet, PDF (27/76 Pages) Integrated Circuit Solution Inc – 1Meg x 8 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM

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Interval Between Read Command
A new command can be executed while a read cycle is in
progress, i.e., before that cycle completes. When the
second read command is executed, after the CAS latency
has elapsed, data corresponding to the new read command
is output in place of the data due to the previous read
command.
The interval between two read command (tCCD) must be at
least one clock cycle.
The selected bank must be set to the active state before
executing this command.
CLK
COMMAND READ A0 READ B0
I/O
DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3
tCCD
READ (CA=A, BANK 0) READ (CA=B, BANK 0)
CAS latency = 2, burst length = 4
Interval Between Write Command
A new command can be executed while a write cycle is in
progress, i.e., before that cycle completes. At the point the
second write command is executed, data corresponding
to the new write command can be input in place of the data
for the previous write command.
The interval between two write commands (tCCD) must be
at least one clock cycle.
The selected bank must be set to the active state before
executing this command.
CLK
COMMAND
tCCD
WRITE A0 WRITE B0
I/O DIN A0 DIN B0 DIN B1 DIN B2 DIN B3
WRITE (CA=A, BANK 0) WRITE (CA=B, BANK 0)
CAS latency = 2, burst length = 4
Integrated Circuit Solution Inc.
27
DR018-0A 07/10/2001