IC42S8200 Datasheet, PDF (15/76 Pages) Integrated Circuit Solution Inc – 1Meg x 8 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM

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OPERATION COMMAND TABLE^(1,2)
Current State Command
Write With DESL
Auto-Precharge
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
RE./SEL.
MRS
Row Precharge DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
RE./SEL.
MRS
Immediately DESL
.ollowing
NOP
Row Active BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
RE./SEL.
MRS
Write
Recovery
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
RE./SEL.
MRS
Operation
CS RAS CAS WE A11 A10 A9-A0
Burst Write Continues, Write Recovery And Precharge H X X X X X X
When Done
Burst Write Continues, Write Recovery And Precharge L H H H X X X
Illegal
L HH L XXX
Illegal
L H L H V V V^&
Illegal
L H L L V V V^&
Illegal⁽¹⁰⁾
L L H H V V V^&
Illegal⁽¹⁰⁾
L LHL VVX
Illegal
L L LHXXX
Illegal
LLLL
OPCODE
No Operation, Idle State After tRP Has Elapsed
HXXXXXX
No Operation, Idle State After tRP Has Elapsed
L HHHX X X
No Operation, Idle State After tRP Has Elapsed
L HH L XXX
Illegal⁽¹⁰⁾
L H L H V V V^&
Illegal⁽¹⁰⁾
L H L L V V V^&
Illegal⁽¹⁰⁾
L L H H V V V^&
No Operation, Idle State After tRP Has Elapsed⁽¹⁰⁾
L LHL VVX
Illegal
L L LHXXX
Illegal
LLLL
OP CODE
No Operation, Row Active After tRCD Has Elapsed
No Operation, Row Active After tRCD Has Elapsed
HXXXXXX
L HHHX X X
No Operation, Row Active After tRCD Has Elapsed
L HH L XXX
Illegal⁽¹⁰⁾
L H L H V V V^&
Illegal⁽¹⁰⁾
L H L L V V V^&
Illegal^(10,14)
L L H H V V V^&
Illegal⁽¹⁰⁾
L LHL VVX
Illegal
L L LHXXX
Illegal
LLLL
OP CODE
No Operation, Row Active After tDPL Has Elapsed
No Operation, Row Active After tDPL Has Elapsed
HXXXXXX
L HHHX X X
No Operation, Row Active After tDPL Has Elapsed
L HH L XXX
Read Start
L H L H V V V^&
Write Restart
L H L L V V V^&
Illegal⁽¹⁰⁾
L L H H V V V^&
Illegal⁽¹⁰⁾
L LHL VVX
Illegal
L L LHXXX
Illegal
LLLL
OP CODE
Integrated Circuit Solution Inc.
15
DR018-0A 07/10/2001