IC42S8200 Datasheet, PDF (18/76 Pages) Integrated Circuit Solution Inc – 1Meg x 8 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM

1+" 5& 
TWO BANKS OPERATION COMMAND TRUTH TABLE^(1,2)
Operation
CS RAS CAS WE A11 A10 A9-A0
Previous State
Next State
BANK 0 BANK 1 BANK 0 BANK 1
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
RE.
MRS
HXXXXXX
L HHHX X X
L HH L XXX
L H L H H H CA⁽³⁾
H H CA⁽³⁾
H L CA⁽³⁾
H L CA⁽³⁾
L H CA⁽³⁾
L H CA⁽³⁾
L L CA⁽³⁾
L L CA⁽³⁾
L H L L H H CA⁽³⁾
H H CA⁽³⁾
H L CA⁽³⁾
H L CA⁽³⁾
L H CA⁽³⁾
L H CA⁽³⁾
L L CA⁽³⁾
L L CA⁽³⁾
L L H H H RA RA
L RA RA
L LHLXHX
XHX
HLX
HLX
LLX
LLX
L L LHXXX
LLLL
OPCODE
Any
Any
R/W/A
I
I/A
I/A
Any
Any
I/A
I/A
R/W/A
I
I/A
R/W
I/A
R/W
R/W/A
A
R/W/A
A
R/W/A
A
R/W/A
A
I/A
R/W
I/A
R/W
I/A
R/W
I/A
R/W
R/W/A
A
R/W/A
A
R/W/A
A
R/W/A
A
I/A
R/W
I/A
R/W
Any
I
I
Any
R/W/A/I I/A
I/A R/W/A/I
I/A R/W/A/I
R/W/A/I I/A
R/W/A/I I/A
I/A R/W/A/I
I
I
I
I
Any Any
Any Any
A
I/A
I
I/A
I/A
A
I/A
I
I/A RP
A
RP
I/A
R
A
R
RP I/A
RP
A
R
I/A
R
A
I/A WP
A
WP
I/A
W
A
W
WP I/A
WP
A
W
I/A
W
A
Any
A
A
Any
I
I
I
I
I/A
I
R/W/A/I I
I
I/A
I R/W/A/I
I
I
I
I
Notes:
1. H: HIGH level input, L: LOW level input, X: HIGH or LOW level input, RA: Row Address, CA: Column
Address
2. The device state symbols are interpreted as follows:
I
Idle (inactive state)
A Row Active State
R Read
W Write
RP Read With Auto-Precharge
WP Write With Auto-Precharge
Any Any State
3. CA: A8,A9 = don't care.
18
Integrated Circuit Solution Inc.
DR018-0A 07/10/2001