HDM8513A Datasheet, PDF (55/67 Pages) Hynix Semiconductor – DVB/DSS Compliant Receiver

6.2 Read Registers
ADDRESS (Hex)
00
Narrowband AGC Accumulator
The current value of the six bit AGC accumulator may be read from this
location.
01, 02, 03
Symbol Timing Frequency Accumulator
The current value of the 20 frequency accumulator in the symbol timing
loop filter may be read from these 3 locations. Bit 7 of address 01 is the
MSB and bit 4 of address 03 is the LSB.
04, 05, 06
Phase Tracking Frequency Accumulator
The current value of the 20 bit frequency accumulator in the carrier phase
loop filter may be read from these 3 locations. Bit 7 of address 04 is the
MSB and bit 4 of address 06 is the LSB.
07
QPSK Lock Status
Bit 0. QPSK Lock Flag
When this bit is set to one, the QPSK demodulator is phase locked.
08
Wide Band AGC Accumulator
This eight bit value represents the most significant bits of the accumulator
in the first order wideband AGC loop. This data only has meaning when
the wideband AGC is in Mode 0.
09, 0A
Sweep Frequency
The 16 bit sweep accumulator is available at this location. Bit 7 of address
09 is the MSB and bit 0 of address 0A is the LSB. Th e receiver frequency
is determined by adding the Sweep Frequency with the carrier frequency
accumulator (read addresses 04, 05 and 06) and the nominal carrier start
frequency (write addresses 04, 05 and 06).
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