HDM8513A Datasheet, PDF (45/67 Pages) Hynix Semiconductor – DVB/DSS Compliant Receiver

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Control Parameters
Bit 0. Binary/Two’s Complement
When this bit is a zero, the system expects the six bit modulation input
samples in two’s complement format, otherwise the input should be in
offset binary format.
Bit 1. Spectrum Invert
When this bit is set to zero, the spectrum of the received signal is
inverted. This has the effect of complementing the in-phase channel
only.
Bit 2. Bias Cancel Enable
When this bit is a one, the internal circuit which cancels DC bias on the I
and Q inputs is enabled. When this function is enabled, it is assumed
that the input signal is scrambled with no significant DC component on
either the I or Q.
Bit 3. Symbol Track Enable
When this bit is set to one, the symbol tracking function is enabled.
When this bit is zero the symbol tracking frequency is forced to the
nominal 20 bit programmed value.
Bit 4. Carrier Track Enable
When this bit is set to one, the carrier phase tracking function is
enabled. When this bit is zero, the carrier frequency is forced to the 20
bit programmed value.
Bit 5. Sweep Hold
When this bit is set to one, the sweeping process is inhibited, and the
nominal carrier frequency remains at the last value.
Bit 6. Narrowband AGC Mode 1 Enable
When this bit is set to one and the narrowband AGC is in Mode 1, the
narrowband AGC self-adjusts to the optimum gain setting. When the bit
is set to zero, the most recent value is held without updating.
Bit 7. Automatic Detection of Spectrum Inversion
When this bit is set to one, the spectrum inversion is detected
automatically.
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