HDM8513A Datasheet, PDF (10/67 Pages) Hynix Semiconductor – DVB/DSS Compliant Receiver

Table 5: Intel 80C88A Read Cycle Timing Parameters (Busmode = 1)
Symbol
tsu1
th1
tpw1
td1
tdoz1
tdoz2
Parameter
Input Address and /CE Setup before /RE Inactive
Input Address and /CE Hold after /RE Inactive
/RE Low Duration
Delay from /CE to DTACK Active
Delay from /RE Inactive to DTACK in Tristate Mode
Delay from /RE Inactive to HI_DATA [7:0] Tristate Mode
Min. Max. Unit
35
-
ns
5
-
ns
200
-
ns
-
35
ns
-
10
ns
10
-
ns
HI_ADDR [4:0]
Valid
/CE
/RE
DTACK
td1
Z
t_pw1
t_h1
Z
t_doz1
HI_DATA[7:0]
t_su1
t_doz2
FIGURE 3: INTEL 80C88A READ TIMING DIAGRAM
Note: HI_ADDR[4:0] is derived from the processor(80C88A) A15-A8 bus and HI_DATA[7:0] is
connected to the AD7 - AD0 bus.
#This page is only for HDM8513AP.
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