HDM8513A Datasheet, PDF (46/67 Pages) Hynix Semiconductor – DVB/DSS Compliant Receiver

10
Reset Functions
Bit 0. Symbol Timing Frequency Accumulator
When this bit is set to zero, the frequency accumulator in the symbol
tracking loop is cleared to zero. This bit must be set to one in normal
tracking operation to implement a second order tracking loop, otherwise
the loop is first order.
Bit 1. Carrier Phase Tracking Frequency Accumulator
When this bit is set to zero, the frequency accumulator in the carrier
phase tracking loop is cleared to zero. This bit must be set to one in
tracking operation to implement a second order loop filter otherwise the
loop is first order.
Bit 2. Wideband AGC Accumulator
When this bit is set to zero, the accumulator in the wideband AGC is
cleared to zero. In normal operation, this bit is set to one. When the
wideband AGC is set to Mode 1, this bit has no effect as the integrator
must be implemented in the external analog circuits.
Bit 3. Narrowband AGC Accumulator
When this bit is set to zero, the accumulator in the narrowband AGC is
cleared to the initial value defined in location 0E. In normal operation,
this bit is set to one.
Bit 4. Unused
Bit 5. Carrier Sweep Function
When this bit is set to zero, the sweep function is disabled and the
carrier frequency is forced to the preset value defined in register
locations 04, 05 and 06.
Bit 6. Viterbi Reset
When this bit is set to zero, the accumulator for the signal quality is
cleared to zero. In normal operation, this bit is set to one.
Bit 7. Reed Solomon Error Counter
When this bit is set to zero, the counters for the number of corrected
errors and the number of uncorrected code words are cleared to zero.
46