HDM8513A Datasheet, PDF (36/67 Pages) Hynix Semiconductor – DVB/DSS Compliant Receiver

5. Signal Description
5.1 Inputs
XTAL1
RESET
AIN_I
AIN_Q
XTAL1 can be configured either for sampling clock input or PLL
reference clock input . The sampling clock rate must be a minimum of
1.33 times the symbol rate of the signal to be processed and at least
equal to the total bandwidth of the signal to be processed.
A low on this signal causes the chip to be initialized. I/O registers are
not cleared by this signal. This signal is asynchronous with respect to
the clock.
Analog Input Signal for I channel. This should be AC coupled with
Analog Input Source via 0.1uF capacitor.
Analog Input Signal for I channel. This should be AC coupled with
Analog Input Source via a 0.1uF capacitor.
5.2 Outputs
VTOP
VBOT
REF_I
REF_Q
DATA [7:0]
Top Reference Voltage Output of about 2.0V. It should be bypassed to
GND by 0.1uF capacitor. External bias voltage can be applied if
necessary.
Bottom Reference Voltage Output of 1.0V. It should be bypassed to
GND by a 0.1uF capacitor. External bias voltage can be applied if
necessary.
Middle Reference Voltage for I Channel. It should be bypassed to GND
by a 0.1uF capacitor.
Middle Reference Voltage for Q Channel. It should be bypassed to
GND by a 0.1uF capacitor.
The eight bit output data is provided in parallel format to be handed to
an MPEG decoder for video and audio decompression.
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