HDM8513A Datasheet, PDF (29/67 Pages) Hynix Semiconductor – DVB/DSS Compliant Receiver

3.7 Clock Generation PLL
An integrated VCO is locked to MxN times a reference frequency provided by a external clock.
Reference ^FRef
ext_clk
Divider
PLL Analog Core
1/2
1/M
FFb
Feedback
Divider
1/N
FIGURE 20: CLOCK SIGNAL GENERATION
1
int_clk
0
enable
This programmable PLL consists of a PLL analog core, a reference divider with a divider ratio M, a
feedback divider with a divider ratio N, and a divider which askes the duty cycle 1/2.
Reference divider and feedback divider are used to synthesize various frequencies from a reference
frequency, fext_clk.
Since PLL synchronizes the frequency and phase of two signals, FRef and FFb,
fext_clk fint_clk
M ⁼N
Internal clock is calculated as follows
fint_clk ₌
N _{fext_clk}
M
The following two PLL modes are provided to control PLL.
(1) PLL Enable mode : The internal clock is connected to the generated clock of the PLL.
(2) PLL Disable mode : The PLL is bypassed and the external clock is directly connected to the
internal clock.
More information can be found on the part of the write register.
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