HDM8513A Datasheet, PDF (17/67 Pages) Hynix Semiconductor – DVB/DSS Compliant Receiver

DATA_CLK
DATA_STB
tsu
t _hd
FRAME_SYNC
DATA_VALID
DATA
n-3 n-2 n-1 n xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx 1 2 3 4
FIGURE 11: OUTPUT TIMING DIAGRAM FOR REGULATED PARALLEL
DATA_CLK
tsu
t _hd
DATA_STB
FRAME_SYNC
DATA [0] _8n-8 xx xx _{8n-7 8n-68n-5 8n-4} xx _{8n-3 8n-28n-1 8n} xx xx xx xx xx xx xx xx 1 2 3 4
FIGURE 12: OUTPUT TIMING DIAGRAM FOR REGULATED SERIAL MODE1
DATA_CLK
tsu
t _hd
FRAME_SYNC
DATA_STB
DATA [0]
8n-8 ^{xx xx} 8n-7 8n-68n-58n-4 ^xx 8n-3 8n-28n-1 8n ^{xx xx xx xx xx xx xx xx 1 2 3 4}
FIGURE 13: OUTPUT TIMING DIAGRAM FOR REGULATED SERIAL MODE2
NOTE : In case of DVB, n is 188
In case of DSS, n is 144
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