HDM8513A Datasheet, PDF (30/67 Pages) Hynix Semiconductor – DVB/DSS Compliant Receiver

3.8 DBS Receiver
The HDM8513A DVB Demodulator including a dual A/D converter and the MPEG-2 decoder provide
the core digital processing technology for a DBS receiver conforming with the DVB standard.
4 80 MHz
Loo p
Filter
Fixed F requencyP LL Control
L-B and
Tuner
4 80 MHz
IF
I
Do wn-
c onve rt e r
Q
BSFC77GV6
AGC 2
AGC 1
3
SL171 0
HDM8513A
L ow
Pa ss
Filter
WB
AGC
Inte rfa c e
DRAM
Da ta
8
8
Conditional
Access
Clock
MPEG-2
Demultiplexer
Video
Audio
Co arse Tuning Step Frequ ency Control
M C68306
(M C68340)
Host Proce ssor
Serial
Interfa ce
FIGURE 21: TYPICAL SET TOP BOX DEMODULATOR
A tuner accepts an L-band RF input from the antenna/LNB assembly located outside the building.
A host processor controls the tuner to the nominal center frequency of the target signal. Baseband
I and Q outputs from the downconverter are applied to an A/D converter pair which is sampled at a
fixed rate, 60MHz as illustrated in this example. The tuner is required to filter the received
baseband signal to a bandwidth less than half the sampling rate, but is not required to perform
matched filtering.
Once the HDM8513A has locked to the target signal, the host processor may read the internal
registers to determine the steady state frequency error. This error would be used to make period
corrections to the programmed frequency of the tuner PLL.
The HDM8513A provides an output which can be used to control the analog AGC in the tuner. This
digital signal must be filtered and amplified before applying it to the AGC control element. When
the loop is closed, the signal applied to the A/D converters is optimally scaled.
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