HDM8513A Datasheet, PDF (53/67 Pages) Hynix Semiconductor – DVB/DSS Compliant Receiver

1F
Clock Generation PLL Control
An integrated VCO is locked to MxN times a reference frequency
provided by a external clock
Bits [4:0]. N Divider ratio
It defines a feedback divider with a divider ratio N. The dafault is 15
(0FH).
Bit 5. M Divider ratio
It defines a reference divider with a divider ratio M. When this bit is set
to 1, the divider ratio M is 4. When this bit is set to 0, the divider ratio M
is 1. The default is 1.
Bit 6. PLL Enable
When this bit is set to 1, the generated clock of the PLL is connected
to the internal clock. When this bit is set to 0, the PLL is bypassed
and the external clock signal is directly connected to the internal
clock. The default is 0.
Bit 7. This bit should be fixed to zero.
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