HDM8513A Datasheet, PDF (54/67 Pages) Hynix Semiconductor – DVB/DSS Compliant Receiver

Example for determination of internal clock
Desired internal clocfkin:t_clk
External clock supplied:
fext_clk
N divider ratio range: 1 – 31 (integer)
M divider
Calculation
riastiaosrafonlgloew: _s1f:ino_tr_{_c}4_lk(in₌tege_MNr)
fext_clk
<Example 1>
Desired internal clock: 60MHz
External clock supplied: 16MHz
N divider ratio range: 1 – 31 (integer)
M divider ratio range: 1 or 4 (integer)
Calculation is as follows: 60 =16 x N/M
Case M =4, N must be 15
Case M =1, N is impossible
Only one possible case exists
<Example 2>
Desired internal clock: 60MHz
External clock supplied: 4MHz
N divider ratio range: 1 – 31 (integer)
M divider ratio range: 1 or 4 (integer)
Calculation is as follows: 60 =4 x N/M
Case M =1, N must be 15
Case M =4, N is impossible
Only one possible case exists.
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