HDM8513A Datasheet, PDF (20/67 Pages) Hynix Semiconductor – DVB/DSS Compliant Receiver

3.2 Variable Rate Demodulator
The block diagram illustrates the overall configuration of the variable rate QPSK demodulator.
Baseband in-phase (I) and quadrature (Q) inputs are applied to the demodulator at a fixed sampling
rate. These digital samples are produced by A/D converters which employ AC coupling to minimize
DC offset.
Symbol Clock
Phase
Accumulator
Symbol
Tracking
Loop Filter
Symbol
Timing
Discriminator
I6
s
Complex
Polyphase
Narrowband
I_o
6
Q
Multiplier
Filters
AG C
Q_o
s
Sine
Cosine
Digital
Oscillator
Carrier
Tracking
Loop Filter
Carrier
Phase
Discriminator
Nominal Carrier
Frequency
Sweep
Control
Lock
Detector
FIGURE 15: DEMODULATOR BLOCK DIAGRAM
Lock
The carrier frequency error associated with these samples is removed digitally during tracking
operations by a complex multiplier and a digitally controlled oscillator, sometimes called a
numerically controlled oscillator (NCO). During initial acquisition, coarse frequency error is
removed by a combination of the digital AGC within the HDM8513A and external analog tuning
circuits.
A polyphase filter performs the root raised cosine filtering of the frequency corrected baseband
samples. This filter, which implements the function of equation (1), is always configured to have an
impulse response duration of 4 symbols regardless of the programmed symbol rate. For low
symbol rates, a large number of samples are used, while for high symbol rates a relatively low
number of samples are processed for each filter output. The outputs of the polyphase filters are
applied to a digital narrowband AGC which insures that the signal is optimally scaled to the Viterbi
decoder to an accuracy of + or - 0.5 dB to insure optimum FEC performance.
y[k] = Σ h[n] x[k-n]
(1)
In addition to optimizing performance of the Viterbi decoder, the digital narrowband AGC also
insures that the performance of the symbol timing and carrier tracking loops is independent of
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