HDM8513A Datasheet, PDF (5/67 Pages) Hynix Semiconductor – DVB/DSS Compliant Receiver

FIGURE 7: MOTOROLA READ TIMING DIAGRAM....................................................................................................14
FIGURE 8: MOTOROLA WRITE TIMING DIAGRAM.................................................................................................15
FIGURE 9: OUTPUT TIMING DIAGRAM FOR NORMAL PARALLEL....................................................................... 16
FIGURE 10: OUTPUT TIMING DIAGRAM FOR NORMAL SERIAL ...........................................................................16
FIGURE 11: OUTPUT TIMING DIAGRAM FOR REGULATED PARALLEL............................................................... 17
FIGURE 12: OUTPUT TIMING DIAGRAM FOR REGULATED SERIAL MODE1.......................................................17
FIGURE 13: OUTPUT TIMING DIAGRAM FOR REGULATED SERIAL MODE2.......................................................17
FIGURE 14: ADC BLOCK DIAGRAM............................................................................................................................ 19
FIGURE 15: DEMODULATOR BLOCK DIAGRAM....................................................................................................... 20
FIGURE 16: NOISE MEASUREMENT CIRCUIT ...........................................................................................................22
FIGURE 17: NOISE ACCUMULATOR AS A FUNCTION OF SNR AND TIME............................................................ 23
FIGURE 18: VITERBI DECODER...................................................................................................................................24
FIGURE 19: REED SOLOMON DECODER.................................................................................................................... 28
FIGURE 20: CLOCK SIGNAL GENERATION................................................................................................................29
FIGURE 21: TYPICAL SET TOP BOX DEMODULATOR............................................................................................ 30
FIGURE 22: MECHANICAL CONFIGURATION ...........................................................................................................32
FIGURE 23: MECHANICAL CONFIGURATION ...........................................................................................................34
FIGURE 24:ANALOG PIN CONNECTION.................................................................................................................... 35
FIGURE 25: CLOCK GENERATION CIRCUIT ..........................................................................................................35
FIGURE 26: I2C WRITE TO THE HDM8513A ...........................................................................................................40
FIGURE 27: I2C READ FROM THE HDM8513A ......................................................................................................... 41
FIGURE A1: SYMBOL TIMING RECOVERY TRANSIENT RESPONSE....................................................................... 59
FIGURE A2: CARRIER PHASE RECOVERY TRANSIENT RESPONSE ........................................................................ 60
FIGURE A3: CARRIERPHASE RECOVERY TRANSIENT RESPONSE WITH LOW SNR ..........................................61
FIGURE A4: ADJACENT CHANNEL INTERFERENCE OF 10 DB, 1.35 SPACING.................................................... 64
FIGURE A5: PERFORMANCE WITH INTERFERER AT DIFFERENT CARRIER SPACINGS .....................................65
FIGURE A6: PERFORMANCE WITH +10 DB INTERFERER......................................................................................66
LIST OF TABLES
TABLE 1: ABSOLUTE MAXIMUM RATINGS ...............................................................................................................8
TABLE 2: DC CHARACTERISTICS.................................................................................................................................8
TABLE 3: DEMODULATOR SPECIFICATIONS.............................................................................................................9
TABLE 4: AC CHARACTERISTICS.................................................................................................................................9
TABLE 5: INTEL 80C88A READ CYCLE TIMING PARAMETERS (BUSMODE = 1)................................................10
TABLE 6: INTEL 80C88A WRITE CYCLE TIMING PARAMETERS (BUSMODE = 1) .............................................11
TABLE 7: INTEL 8051 READ CYCLE TIMING PARAMETERS (BUSMODE = 1)......................................................12
TABLE 8: INTEL 8051 WRITE CYCLE TIMING PARAMETERS (BUSMODE = 1)................................................... 13
TABLE 9: MOTOROLA READ CYCLE TIMING PARAMETERS (BUSMODE =0).................................................... 14
TABLE 10: MOTOROLA WRITE CYCLE TIMING PARAMETERS (BUSMODE =0).................................................15
TABLE 11: OUTPUT TIMING....................................................................................................................................... 16
TABLE 12: EXAMPLE OF ACQUISITION TIMING.....................................................................................................26
TABLE 13: I2C SLAVE ADDRESS..................................................................................................................................41
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