HY5DU283222AQ Datasheet, PDF (47/51 Pages) Hynix Semiconductor – 128M(4Mx32) GDDR SDRAM

Bank Read Access
/CK
CK
CKE
tCK
tIH
tIS
tCH tCL
CMD
NOP
RA, CA
RA
ACT
tIS tIH
RA
RA
NOP
NOP
NOP
AP
BA0,BA1
DM
RA
tIS tIH
Bank x
tRCD
tRAS
Case1:
tAC/tDQSCK=min
DQS
DQ
CASE2 :
tAC/tDQSCK=max
DQS
DQ
HY5DU283222AQ
READ
Col n
NOP
tIS tIH
DIS AP
Bank x
tRC
CL=2
PRE
NOP
NOP
All Bank
One Bank
Bank x
tRP
ACT
RA
RA
RA
Bank x
tRPRE
tLZ min
tDQSCK min
tRPST
tHZ min
DQ n
tLZ min
tAC min
tRPRE
tLZ max
tDQSCK max
tRPST
tHZ max
DQ n
tLZ max
tAC max
DQ n = Data out from column n
Burst length = 4 in the case shown
3 subsequent elements of Data out are provided in the programmed order following DQ n
DIS AP = Disable Autoprecharge
* = * “ Don’t Care”, if AP is high at this point
PRE = Precharge, ACT=Active, RA=Row Address, BA=Bank Address
NOP commands are shown for ease of illustration; other commands may be valid at these times
Note that tRCD > tRCD min so that the same timing applies if Autoprecharge is enabled (in which case tRAS would be limiting)
Rev. 0.2 / Sep. 2003
Don’t care
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