HY5DU283222AQ Datasheet, PDF (32/51 Pages) Hynix Semiconductor – 128M(4Mx32) GDDR SDRAM

HY5DU283222AQ
Auto Refresh and Precharge All command
When /CS=L, /RAS=L, /CAS=L and /WE=H, DDR SDRAM enter into Auto Refresh mode, which executes refresh oper-
ation with internal address increment. AREF command can be initiated at the rising edge of the clock as other com-
mands do. Before entering Auto Refresh mode, all banks must be in a precharge state and AREF command can be
issued after tRP period from Precharge All command.
Fig.18. Auto Refresh and Precharge All command
/CLK
CLK
tRP
CMD
DQS
DQ
CKE
Hi-Z
PRECHG
Precharge all
Held High
AUTOREF
tRC = tRAS + tRP
ACT
Self Refresh Entry and Exit
When CKE=L, /CS=L, /RAS=L, /CAS=L and /WE=H, DDR SDRAM enter into Self Refresh mode, which executes self
refresh operation with internal address increment. Before issuing Self Refresh command, all banks must be in a pre-
charge state and CKE must be low. SREF command can be initiated at the rising edge of the clock as other commands
do. Because the clock buffer and internal DLL circuit are disabled during self refresh state, Self Refresh Exit (SREX)
should guarantee the stable input clock. Therefore, a minimum of 200 cycles of stable input clock, where CKE is held
high, is required to lock the internal DLL circuit of DDR SDRAM. A minimum tPDEX (Power Down Exit Time) must be
met before entering SREX command.
Fig.19. Self Refresh Entry and Exit
/CLK
CLK
CMD PRECHG
Precharge all
CKE
SREF
DESL
SREX
Min. 200 clock cycles
tXSC
tP D E X m in
ACT
Rev. 0.2 / Sep. 2003
32