HY5DU283222AQ Datasheet, PDF (28/51 Pages) Hynix Semiconductor – 128M(4Mx32) GDDR SDRAM

HY5DU283222AQ
Burst Read with Autoprecharge
If a Read with Autoprecharge command is detected by memory component in CLK(n), then there will be no commands
presented to this bank until CLK(n+BL/2+tRP). Internal precharging action will happen in CLK(n+BL/2).
Fig.10. Burst Read with Autoprecharge
/C L K
CLK
CMD
DQS
DQ
READ (A)
w/ Autopcg
BL/2 + tRP
ACT
A0 A1 A2 A3
Early term ination is illegal here
Burst length =4, CAS latency =2
Burst Write with Autoprecharge
If a Write with Autoprecharge command is detected by memory component in CLK(n), then there will be no commands
presented to this bank until CLK(n+BL/2+1+tDPL+tRP). Last Data in to Precharge delay time (tDPL) is needed to
guarantee the last data has been written. tDPL is measured with respect to rising edge of clock where last falling edge
of data strobe (DQS) and DQ data has elapsed. Internal precharging action will happen in CLK(n+BL/2+1+tWR) as
shown in Fig.11.
Fig.11. Burst Write with Autoprecharge
/CLK
CLK
CMD
DQS
W RITE (A)
w/ Autopcg
DQ
A0 A1 A2 A3
Burst length =4, CAS latency =2
tDPL
tRP
ACT
Rev. 0.2 / Sep. 2003
28