HY5DU283222AQ Datasheet, PDF (31/51 Pages) Hynix Semiconductor – 128M(4Mx32) GDDR SDRAM

HY5DU283222AQ
DM masking (Write)
DM command masks burst write data with reference to data strobe signal and it is not related with read data. DM com-
mand can be initiated at both the rising edge and the falling edge of the DQS. DM latency for write operation is zero.
For x16 data I/O, DDR SDRAM is equipped with LDM and UDM which control lower byte (DQ0~DQ7) and upper byte
(DQ8~DQ15) respectively.
Fig.16. DM masking (Write)
/CLK
CLK
CMD
DQS
DQ
WRITE (A)
tDQSS
Masked
A0 A1
Masked
A2 A3
DM
Burst length =4, CAS latency =2
DM can mask write data with reference to DQS
DM write latency = 0
Burst Stop command (Read)
When /CS=L, /RAS=H, /CAS=H and /WE=L, DDR SDRAM enter into Burst Stop mode, which bursts stop read data and
data strobe signal with reference to clock signal. BST command can be initiated at the rising edge of the clock as other
commands do. BST command is valid for read operation only. BST latency for read operation is the same as CL.
Fig.17. Burst Stop command (Read)
/C L K
CLK
CMD
READ (A) BST (A)
DQS
DQ
Burst length =4, CAS latency =2
Burst DQS & DQ stop
A0 A1
Rev. 0.2 / Sep. 2003
31