HY5DU283222AQ Datasheet, PDF (27/51 Pages) Hynix Semiconductor – 128M(4Mx32) GDDR SDRAM

HY5DU283222AQ
Burst Read terminated by another Burst Write
Write command terminates the previous Read command with the insertion of Burst Stop command that disables the
previous Read command. The Burst Stop command interrupts bursting read data and data strobe signal with the same
latency as CAS Latency (CL). The minimum delay for Write command after Burst Stop command is RU{CL} clocks irre-
spective BL. The Burst Stop command is valid for Read command only.
Fig.8. Burst Read terminated by another Burst Write
/CLK
CLK
CMD
DQS
tCCD
READ (A) BST (A)
WRITE (B)
Burst DQS & DQ stop
DQ
Burst length =4, CAS latency =2
A0 A1
B0 B1 B2 B3
W rite data starts
Burst Write terminated by another Burst Read
Read command terminates the previous Write command and the new burst read starts as shown in Fig.9. The mini-
mum write to read command delay is 2 clock cycle irrespective of CL and BL. If input write data is masked by the Read
command, DQ and DQS input are ignored by the DDR SDRAM. It is illegal for a Read command to interrupt a Write
with autoprecharge command.
Fig.9. Burst Write terminated by another Burst Read
/CLK
CLK
CMD
DQS
DQ
WRITE (A)
READ (B)
Masked
A0 A1 A2 A3
DM
Burst length =4, CAS latency =2
B0 B1 B2 B3
Rev. 0.2 / Sep. 2003
27