HY5DU283222AQ Datasheet, PDF (24/51 Pages) Hynix Semiconductor – 128M(4Mx32) GDDR SDRAM

HY5DU283222AQ
Burst Read followed by Burst Read
Back to back read operation in the same or different bank is possible as shown in Fig.2. Following first Read command,
consecutive Read command can be initiated after BL/2 ticks of clock. In other words, minimum earliest possible Read
command that does note interrupt the previous read data, can be issued after BL/2 clock is met. When Read(B) data
out starts, data strobe signal does not transit to Hi-Z but toggle high and low for Read(B) data.
Fig.2. Burst Read followed by Burst Read
/CLK
CLK
CMD
READ (A)
READ (B)
DQS
DQ
Burst length =4, CAS latency =2
A0 A1 A2 A3 B0 B1 B2 B3
READ(B) data out starts
Burst Write followed by Burst Write
Back to back write operation in the same or different bank is possible as shown in Fig.3. Following first Write com-
mand, consecutive Write command can be initiated after BL/2 ticks of clock. In other words, minimum earliest possible
Write command that does note interrupt the previous write data, can be issued after BL/2 clock is met. When Write(B)
data in starts, data strobe signal does not transit to Hi-Z but toggle high and low for Write(B) data. Though the timing
shown in Fig.3. is based on tDQSS=0.75*tCK, minimum number of clock of BL/2 for back to back write can be applied
when tDQSS=1.25*tCK.
Fig.3. Burst Write followed by Burst Write
/CLK
CLK
CMD
DQS
WRITE (A)
tDQSS
WRITE (B)
DQ
A0 A1 A2 A3 B0 B1 B2 B3
Burst length =4, CAS latency =2
W RITE(B) data in starts
Rev. 0.2 / Sep. 2003
24