HY5DU283222AQ Datasheet, PDF (29/51 Pages) Hynix Semiconductor – 128M(4Mx32) GDDR SDRAM

HY5DU283222AQ
Precharge command after Burst Read
The earlist Precharge command can be issued after Read command without the loss of data is BL/2 clocks. The Pre-
charge command can be given as soon as tRAS time is met. Fig.12 shows the earlist possible Precharge command can
be issued for CL=2 and BL=4.
Fig.12. Precharge command after Burst Read
/CLK
CLK
CMD
READ (A)
DQS
DQ
Burst length =4, CAS latency =2
tRP
PRECHG
ACT
A0 A1 A2 A3
Earliest precharge time without losing read data
Precharge command after Burst Write
The earliest Precharge command can be issued after Write command without the loss of data is (BL/2+1+tDPL) ticks
of clocks. The Precharge command can be given as soon as tRAS time is met. Fig.13 shows the earliest possible Pre-
charge command can be issued for CL=2 and BL=4.
Fig.13. Precharge command after Burst Write
/CLK
CLK
CMD
WRITE (A)
DQS
DQ
A0 A1 A2 A3
Burst length =4, CAS latency =2
PRECHG
tDPL
tRP
ACT
Issuing precharge here allows
completion of entire burst write
tDPL is counted with respect to CLK rising edge
after last falling edge of DQS and DQ data has elapsed
Rev. 0.2 / Sep. 2003
29