HY5DU283222AQ Datasheet, PDF (30/51 Pages) Hynix Semiconductor – 128M(4Mx32) GDDR SDRAM

HY5DU283222AQ
Precharge termination of Burst Read
The Burst Read (with no Autoprecharge) can be terminated earlier using a Precharge command as shown in Fig.14.
This terminates read data when the remaining elements are not needed. It allows starting precharge early. The Pre-
charge command can be issued any time after Burst Read command when tRAS time is met. Activation or other com-
mands can be initiated after tRP time.
Fig.14. Precharge termination of Burst Read
/CLK
CLK
CMD
tRP
READ (A) PRECHG
ACT
DQS
DQ
Burst length =4, CAS latency =2
A0 A1
Precharge time can be issued here with tRASmin being met
Precharge termination of Burst Write
The Burst Write (with no Autoprecharge) can be terminated earlier using a Precharge command along with the Write
Mask (DM) as shown in Fig.15. This terminates write data when the remaining elements are not needed. It allows
starting precharge early. Precharge command can be issued after Last Data in to Precharge delay time (tDPL). tDPL is
measured with respect to rising edge of clock where last falling edge of data strobe (DQS) and DQ data has elapsed.
DM should be used to mask the remaining data (A2 and A3 for this case). tRAS time must be met to issue the Pre-
charge command.
Fig.15. Precharge termination of Burst Write
/CLK
CLK
CMD
DQS
DQ
WRITE (A)
tDQSS
PRECHG
tDPL
Masked
A0 A1 A2 A3
ACT
tRP
tDPL is counted with respect to CLK rising edge
after last falling edge of DQS and DQ data has elapsed
DM
Burst length =4, CAS latency =2
Rev. 0.2 / Sep. 2003
W rite burst is term inated early. DM is asserted
to prevent locations of A2 and A3
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