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| HY5DU283222AQ Datasheet, PDF (44/51 Pages) Hynix Semiconductor – 128M(4Mx32) GDDR SDRAM | |||
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Self Refresh Mode
HY5DU283222AQ
/CK
CK
CKE
COMMAND
tCK
tCH
tCL
tIS tIH
tIS
tIS tIH
NOP
AR
ADDR
clock must be stable before
exiting Self Refresh mode
tIS
NOP
VALID
tIS tIH
VALID
DQS
DQ
DM
tRP*
Enter
Self Refresh
Mode
tXSNR/
tXSRD**
Exit
Self Refresh
Mode
Donât Care
* = Device must be in the âAll banks idleâ state prior to entering Self Refresh mode
** = tXSNR is required before any non-READ command can be applied, and tXSRD (200 cycles of CK)
are required before a READ command can be applied.
Rev. 0.2 / Sep. 2003
44
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